A transistor in which an SOI (Silicon on Insulator) substrate is used can reduce parasitic capacitance by a large amount than can a transistor in which a bulk silicon Si (silicon) substrate is used, and therefore achieves an increase in operation speed and a reduction in electric power consumption.
Among methods of producing an SOI substrate, a generally well-known method is the one in which a single-crystal Si layer is directly transferred onto an insulating layer by employing hydrogen ions implantation. An example of such a method is the Smart Cut (Registered Trademark) method.
However, since such a general SOI substrate is made from an Si substrate (wafer) having a size of approximately 6 inches Φ to 8 inches Φ, it was difficult to produce a large SOI substrate.
In view of the circumstances, as disclosed in Patent Literatures 1 through 6 for example, there has recently been development of technologies for producing a large-surface-area SOI substrate by a plurality of Si wafers are combined with a large glass substrate and then transferring an Si thin film by use of the Smart Cut method.
According to Patent Literature 3, a plurality of semiconductor substrates are combined with a single large glass substrate.
According to Patent Literature 3, silicon substrates are provided in respective four substrate placement regions (which are concave parts) that are provide on a substrate supporting base of a device. Then, a single large base substrate is provided so as to cover the silicon substrates provided in the respective four concave parts. Since the base substrate is large, the base substrate is supported by convex parts surrounding the respective four substrate placement regions so that the flexure of the base substrate is prevented.
Note that a plurality of substrate supporting mechanisms are provided (i) on respective bottom parts of the silicon substrates and (ii) so as to penetrate through the substrate supporting base. The silicon substrates, which are provided in the respective substrate placement regions, are lifted/lowered by the substrate supporting mechanisms. Then, when lifted, the silicon substrates come into contact with and pressed against the base substrate. This is how the plurality of silicon substrates are combined with the base substrate.
According to Patent Literature 3, a plurality of silicon substrates are thus combined at once with a single base substrate which is a large glass substrate.
Since the base substrate is supported by the convex parts surrounding the four substrate placement regions of the substrate supporting base as described above, each of the silicon substrates are combined with the base substrate apart from the other silicon substrates.
Patent Literatures 4 and 5 each disclose a method in which (i) silicon substrates are provided in respective trays each having a concave form and then (ii) silicon layers, which have been separated from the silicon substrates, are transferred onto a single base substrate.
The method disclosed in Patent Literatures 4 and 5 for producing an SOI substrate will be described below with reference to FIG. 21.
FIG. 21 is a view for describing the method, disclosed in Patent Literatures 4 and 5, of producing an SOI substrate.
As illustrated in (a) of FIG. 21, silicon substrates 812 are provided in respective concave parts which are provided on a tray 810 and are provided apart from one another.
Note that in a case where the silicon substrates 812 are to be provided on the concave parts by machine or the like, it is necessary to use a jig to hold or vacuum-hold the silicon substrates 812 by their side surfaces or back surfaces, so that combining surfaces of the silicon substrates 812 will not become dirty. Therefore, in order to secure clearance through which the jig is to be removed after providing the silicon substrates 812, the concave parts provided on the tray 810 are arranged apart from one another.
Then, as illustrated in (b) of FIG. 21, breakable regions 813 (fragile layers) are formed at a predetermined depth of the silicon substrates 812 by implanting hydrogen ions 821 in the silicon substrates 812 provided in the concave parts.
Then, as illustrated in (c) of FIG. 21, a base substrate 814, which is a single, common, large glass substrate, is combined with front surfaces (opposite surfaces facing the tray 810) of the silicon substrates 812 by applying pressure. In so doing, the base substrate 814 and the tray 810 are inverted.
Then, by heating, semiconductor layers 815 are separated from remaining parts of the silicon substrates 812 at the breakable regions 813. This allows the plurality of semiconductor layers 815 to be transferred onto the base substrate 814.
Then, as illustrated in (d) of FIG. 21, front surfaces of the semiconductor layers 815 are made flat by irradiating the front surfaces with a laser beam.
According to Patent Literatures 6 and 7, the single base substrate 814 is thus combined with the plurality of semiconductor layers 815.
Since the silicon substrates 812 are provided apart from one another on the tray 810, the semiconductor layers 815 are combined with the base substrate 814 apart from one another accordingly.
Note that the semiconductor layers 815 provided on the base substrate 814 are each required to be a thin film in order to (i) bring about a desired TFT characteristic (low off-leakage current) and (ii) secure coverage to be provided over the semiconductor layer 815. However, if a thin semiconductor layer 815 (which is made thin by forming a breakable region 813 at a shallow depth) is directly transferred to the base substrate 814, then such a thin semiconductor layer 815 becomes prone to a hole(s), and therefore causes a decrease in yield.
Hence, semiconductors, which have a thickness thicker than a desired thickness, are transferred in advance onto the base substrate 814. Then, a laser beam is used to irradiate the semiconductor layers so as to cause front surfaces of the semiconductor layers to be flat (see (d) of FIG. 21), and then the semiconductor layers are subjected to a dry etching process (which is an etch back process for thinning the semiconductor layers, and is hereinafter referred to as “etch back process”). This causes the semiconductor layers to be thin.
The etch back process is carried out by (i) placing a base substrate, on which semiconductor layers are provided, in a chamber, (ii) introducing process gas into the chamber, and then (iii) generating plasma on front surfaces of the base substrate.
Patent Literature 6 discloses a method in which (i) a plurality of silicon substrates are provided on a base substrate, (ii) the silicon substrates are each covered with a covering, (iii) the silicon substrates are broken apart at their respective breakable regions, and then (iv) silicon layers are transferred onto the base substrate.
By separating the silicon substrates at their respective breakable regions after covering each of the silicon substrates with a covering, semiconductor layers transferred onto the base substrate are prevented from being damaged by the other parts of the silicon substrates which parts could otherwise shift sideways after being broken apart from the semiconductor layers.